DDR3

Memory Updated Sep 2026

DDR3 SDRAM

The fundamentals of DDR3 SDRAM architecture — voltage, prefetch, bank topology, on-die termination, clocking, and how it handles (and doesn't handle) bus errors.

!!! info "The basic DRAM cell"
DDR3 stores data the same way every DDR generation does: one transistor, one capacitor per bit, refreshed periodically because the capacitor leaks charge. Everything below describes the machinery built around that cell to get data in and out reliably at DDR3's operating speeds.

1. Overview

!!! abstract "Core specs"
Introduced 2007. Operates at 1.5 V (1.35 V for the low-voltage DDR3L variant). Data rates from 800 to 2133 MT/s. Standard desktop DIMM uses 240 pins.

Feature	DDR3
Introduction	2007
Typical voltage	1.5 V (1.35 V DDR3L)
Data rates	800–2133 MT/s
DIMM pins (desktop)	240
Prefetch / burst length	8n / BL8
Banks	8, no bank groups
Channel width per DIMM	Single 64-bit channel
Signaling	SSTL_15

CPU
  │
Memory Controller
  │
Address/Command Bus
  │
DRAM Chips

Inside the DRAM chip:

Rows
──────────────
[row]
      │
      ▼
Sense Amplifiers
      │
      ▼
Column Select
      │
      ▼
I/O Drivers

2. Bank Topology

DDR3 has 8 banks and no bank groups. Each bank can service one command at a time; after an activate, it needs a recovery period (tRC) before it can be activated again. With only 8 banks and no grouping structure, the controller has fewer ways to interleave accesses across independent banks than later generations — DDR3 works well for predictable, sequential access patterns, but bank conflicts become more of a limiting factor as core counts and access parallelism rise.

DDR3 uses a single 64-bit channel per DIMM — one shared command/address bus and one 64-bit data path, fully parallel.

3. Package-Level Details

!!! info "Package vs. DIMM"
A DIMM is a board populated with several DRAM packages. The specs below describe the DRAM IC package itself — the FBGA chip soldered or reflowed onto the module.

Aspect	DDR3
Package type	78/96-ball FBGA, ~0.8 mm pitch
Max practical die density	4–8 Gb
Multi-die packaging	Dual-die package (DDP), wire-bonded
Command pins	Discrete RAS#/CAS#/WE#
Added reliability pins	ODT pin only
Power delivery to package	From board VRM

Data width per chip (x4 / x8 / x16): x4 for high-capacity ECC/RDIMM setups, x8 for typical consumer DIMMs, x16 for low chip-count modules — the same convention every DDR generation follows.

4. Power Delivery

DDR3 draws its operating voltage regulation directly from the motherboard VRM (voltage regulator module) — there's no on-module power management. This keeps the DIMM itself simple, and it means a power-delivery fault is a board-level issue, separately diagnosable from the memory module itself.

Motherboard VRM
      │
  DRAM Chips

5. On-Die Termination (ODT)

!!! abstract "Why termination exists"
At multi-hundred-megatransfer speeds, data and command lines behave like transmission lines. An unterminated line reflects signal energy back from the open end of the trace, and that reflection corrupts the next bit. ODT is switchable resistance built into the DRAM die (and host controller) that absorbs the reflection.

DDR3 is the generation where ODT became a standard, fully-featured mechanism (it existed in a more basic form in DDR2). Each DQ/DQS pin has a resistor network switchable between several values — commonly 240 Ω, 120 Ω, 60 Ω — set via mode register commands. The controller selects the value depending on whether the rank is being written to, read from, or idle while a neighboring rank is active.

ODT mode	Purpose
`RTT_NOM`	Default termination during normal (non-write) operation
`RTT_WR`	Termination applied specifically during writes to that rank

DDR3 does not have dynamic ODT (mid-burst value switching) or command/address-bus termination — both arrive in later generations.

6. DLL (Delay-Locked Loop) & Clocking

!!! abstract "Core idea"
The DLL phase-aligns the DRAM's internal DQ/DQS output timing with the external clock, compensating for propagation delay through the die's I/O circuitry. Without it, read data strobes drift out of phase with the clock as frequency increases and the controller can't reliably latch data.

DDR3 uses an on-die DLL, active during normal operation. It must relock after the chip exits a low-power state like self-refresh — tDLLK (DLL lock time) is a defined timing parameter, and the chip cannot be reliably read from until the DLL has relocked. There is no DLL-off low-power mode in DDR3 — that arrives with DDR4.

7. Bus Error Handling

DDR3 has comparatively little built-in error protection by later-generation standards:

No on-die ECC. Whatever's stored in the array is stored as-is; there's no internal parity computed and checked entirely inside the chip.
No write CRC. A write burst isn't independently checksummed and verified by the DRAM.
No command/address parity. A corrupted address bit during a command transfer has no built-in detection mechanism at the DRAM level.
No read-path protection. As with every DDR generation, the read path (DRAM → controller) has no native CRC.

The only way to get error correction on DDR3 is a system-level ECC-DIMM — a module with an extra data lane (typically 72 bits wide instead of 64) where the memory controller computes and checks its own ECC. This is optional, board/module-level, and entirely separate from anything on the DRAM die itself.

8. Bandwidth Reference

Assuming a single 64-bit channel:

Memory	Peak bandwidth
DDR3-800	6.4 GB/s
DDR3-1600	12.8 GB/s
DDR3-2133	17.0 GB/s

9. Study Checklist

[ ] Explain why capacitor leakage requires periodic row refresh
[ ] State DDR3's voltage, prefetch, and bank count
[ ] Explain why DDR3 has no bank groups and what that means for access parallelism
[ ] Explain what RTT_NOM and RTT_WR control
[ ] Explain the DLL's role and why tDLLK exists
[ ] Explain why DDR3 has no on-die ECC and what the only available error-correction option is
[ ] Describe the FBGA package basics (ball count, pitch, DDP multi-die packaging)

References: DDR3 JEDEC specification (JESD79-3).