DDR4 / DDR5 / DDR6 — Focused Comparison
A narrower companion to the full DDR3–DDR6 architecture page: this one drops DDR3 and focuses on the three generations most relevant to current and near-future system design — the mature, deployed DDR4, the current mainstream DDR5, and the still-drafting DDR6.
!!! warning "DDR6 is not ratified — read this before anything else"
As of this writing, JEDEC has published the mobile companion spec, LPDDR6 (JESD209-6), in July 2025 — the first DDR6-era standard to actually ship. The desktop/server DDR6 specification itself is still in platform validation with Intel, AMD, NVIDIA, and the major DRAM manufacturers (Samsung, SK hynix, Micron). Numbers below vary across pre-ratification sources — most notably the exact subchannel width and final operating voltage — so every DDR6 figure on this page is directional, not authoritative. Commercial timeline estimates cluster around enterprise/server availability in 2026 and broader consumer availability in 2027–2028, but treat that as a rough industry consensus, not a JEDEC commitment.
1. Generational Snapshot
| Feature | DDR4 | DDR5 | DDR6 (draft) |
|---|---|---|---|
| Introduction | 2014 | 2020 | Draft finalizing; server ~2026, consumer ~2027–2028 |
| Typical voltage | 1.2 V | 1.1 V | Further reduced vs. DDR5 — exact figure not yet finalized |
| Base data rates | 1600–3200 MT/s | 4800–8800+ MT/s | 8,800–17,600 MT/s roadmap; OC grades reportedly targeting 21,000+ MT/s |
| DIMM pins (desktop) | 288 | 288 | New pinout/connector — not backward compatible with DDR5 sockets |
| Physical form factor | Standard DIMM | Standard DIMM, on-module PMIC | New connector; CAMM2 favored for client/compact systems, server format still finalizing |
| Prefetch / burst length | 8n / BL8 | 16n / BL16 | Expected to extend further — not yet published |
| Banks | 16 in 4 bank groups | 32 in 8 bank groups | Further increase expected — count not yet published |
| Subchannels per DIMM | Single 64-bit channel | Two 32-bit subchannels | Reported as four subchannels; per-subchannel width cited inconsistently (16-bit vs. 24-bit) across sources |
| Max practical die density | 16 Gb | 24–32 Gb+ | Roadmap target up to 128 Gb per die |
| On-die ECC | Not present (optional ECC-DIMM only) | Mandatory baseline | Expected to continue as mandatory baseline |
2. What Actually Changes Between DDR4 → DDR5 → DDR6
!!! abstract "The pattern to notice"
Every jump follows the same playbook: split the channel into more, narrower pieces; add more banks to keep the wider prefetch fed; push more reliability circuitry onto the die; and move more power regulation onto the module itself. DDR6 isn't a new playbook — it's the same one applied more aggressively because the target data rate roughly doubles again.
2.1 Channel splitting
- DDR4 — one 64-bit channel per DIMM, fully parallel.
- DDR5 — splits into two independent 32-bit subchannels, each with its own command/address bus. This doubles the number of outstanding operations a single module can service, which matters most for small, random accesses (the access pattern that dominates most real workloads, as opposed to long sequential streams).
- DDR6 (draft) — reported drafts push this to four subchannels per DIMM. The exact per-subchannel width isn't settled in public pre-ratification coverage (some sources say 16-bit, others 24-bit), which is itself a useful signal: this is genuinely still being finalized, not just under-reported.
DDR4 DIMM: [========== 64-bit channel ==========]
DDR5 DIMM: [==32-bit==][==32-bit==]
DDR6 DIMM [~16-24][~16-24][~16-24][~16-24]
(draft):
2.2 Bank groups
DDR4 introduced bank grouping (16 banks / 4 groups) specifically to solve the problem of a single bank not being able to service commands fast enough for the wider bursts modern controllers issue — tCCD_S (different group) is faster than tCCD_L (same group), so the controller interleaves across groups to keep the pipe full. DDR5 doubled this again (32 banks / 8 groups) because its 16n prefetch needs even more banks in flight. DDR6's roadmap is expected to continue this trend, though the specific bank/group count hasn't been published — the pattern (wider prefetch → more banks needed to feed it) is the reliable part, the exact number isn't yet.
2.3 Density and package
DDR4 tops out around 16 Gb per die in practical production; DDR5 pushes to 24–32 Gb+ using the same TSV/3DS stacking approach DDR4 introduced for multi-die packages. DDR6's headline density roadmap target — up to 128 Gb per die — is a genuinely large jump, and it's the reason forecasts mention 64 GB+ consumer sticks and 256 GB+ server modules. This is a capacity story, not a bandwidth one: it rides on the same die-stacking trend already established, just pushed further.
2.4 Power delivery
DDR4 draws voltage regulation from the motherboard VRM, same as every generation before it. DDR5's biggest structural change was moving that regulation onto the module itself via an on-DIMM PMIC — better local regulation at higher speeds, but a new single point of failure (a dead PMIC takes down the whole module, where a DDR4 board-level VRM issue was separately diagnosable). DDR6 drafts are expected to keep this on-module PMIC model, likely with more regulation channels to serve four subchannels instead of two — though the exact topology isn't published yet.
3. Reliability and Error Handling
!!! danger "Two separate error domains, same as always"
On-die ECC protects data sitting in the DRAM array. CRC and parity protect data in transit on the bus. A bit can be correct in the array, get corrupted en route to the controller, and on-die ECC never sees it — it runs before data leaves the chip.
| Mechanism | DDR4 | DDR5 | DDR6 (draft) |
|---|---|---|---|
| On-die ECC (array-side) | Not present | Mandatory baseline (SECDED-equivalent, vendor-specific code) | Expected to continue as mandatory — DDR6's much higher target density makes this more necessary, not less |
| Write CRC (host → DRAM) | Introduced | Retained | Expected to continue — mismatch still triggers ALERT# and a controller retry |
| Command/address parity | Introduced (PAR pin) | Retained, further encoded | Expected to continue in concept; exact scheme TBD given further command-bus encoding |
| Read-path CRC (DRAM → controller) | None | None — this is the standing weak link; protection depends entirely on system-level ECC | Unconfirmed. No pre-ratification source surveyed for this page confirms a native read-path CRC in DDR6 — assume the same weak link persists until the ratified spec says otherwise |
The read path is worth dwelling on because it's the one place all three generations plausibly share the same gap. Writes are protected because the controller still holds the original data and can simply retry on a CRC mismatch. Reads have no equivalent fallback in the base spec — a bit flip on the read bus that nothing else catches is delivered to the CPU as silent corruption unless the system has a separate, wider ECC-capable DIMM (the classic 72-bit-instead-of-64-bit module) computing its own check. If DDR6 closes this gap, it would be a genuinely notable reliability improvement over both prior generations — but it isn't confirmed as of this writing.
One data point worth tracking: LPDDR6 (JESD209-6), the already-ratified mobile sibling spec, is explicitly documented as adding enhanced reliability and security features over LPDDR5. That's a reasonable signal for where desktop/server DDR6 is headed — but LPDDR6 and DDR6 are related, not identical, specifications, so it isn't a guarantee.
4. Bandwidth
Assuming each DIMM sums to a 64-bit-equivalent total channel width — true for DDR4's single 64-bit channel and DDR5's 2×32-bit split, and assumed here for DDR6's reported 4-subchannel split following the same pattern:
| Memory | Peak bandwidth |
|---|---|
| DDR4-3200 | 25.6 GB/s |
| DDR5-5600 | 44.8 GB/s |
| DDR5-6400 | 51.2 GB/s |
| DDR5-8800 | 70.4 GB/s |
| DDR6-8800 (draft) | ~70.4 GB/s |
| DDR6-17600 (draft) | ~140.8 GB/s by the same formula (some published previews cite ~134.4 GB/s — treat the exact figure as pre-ratification) |
!!! note "Bandwidth, not latency, is the headline"
DDR5's latency in nanoseconds isn't dramatically lower than DDR4's — internal timing parameters scaled up along with clock speed, so the real-world win is throughput and parallelism, not reduced latency. Early DDR6 coverage suggests the same pattern will repeat at the next step up: expect roughly double the bandwidth of top-end DDR5, not a nanosecond-latency breakthrough. Nothing here is confirmed until the ratified spec publishes timing parameters.
5. Practical Takeaways
!!! abstract "If you're designing or specifying today"
- DDR4 is legacy but still deployed at scale — mature tooling, well-understood failure modes, no on-die ECC (pair with an ECC-DIMM if data integrity matters).
- DDR5 is the current mainstream choice — on-die ECC is now baseline, the on-module PMIC changes your failure-domain thinking, and the two-subchannel split rewards small-random-access-heavy workloads.
- DDR6 is not a today decision. Treat every number in this document as a planning input, not a design input, until JEDEC ratifies the spec. If you're doing forward-looking architecture work, the safe assumptions are: roughly double DDR5's peak bandwidth, meaningfully higher per-die density, a new non-backward-compatible connector, and continuation (not reversal) of DDR5's on-die ECC and on-module PMIC trends. Everything more specific than that should be checked against the ratified spec before it goes into a real design.
6. Study Checklist
- [ ] State the voltage, prefetch, and bank-group progression across DDR4 → DDR5 → DDR6 (draft)
- [ ] Explain why DDR5 splits each DIMM into two 32-bit subchannels, and why DDR6 drafts go further to four
- [ ] Explain why bank groups exist and why wider prefetch drives the need for more of them
- [ ] Explain the DDR5 on-die ECC mandatory baseline — what it protects and what it doesn't
- [ ] Trace what happens when write CRC or C/A parity detects an error (
ALERT#→ retry) - [ ] Explain why the read path has no native CRC in DDR4 or DDR5, and why DDR6's status there is still unconfirmed
- [ ] Explain the DDR5 on-module PMIC change and its failure-domain implications, and what's expected to carry into DDR6
- [ ] Explain what LPDDR6 (JESD209-6, ratified July 2025) does and doesn't tell you about desktop/server DDR6
- [ ] Identify which DDR6 numbers in this document are well-supported vs. genuinely unsettled as of publication
References: DDR4/DDR5 JEDEC specifications. DDR6 figures drawn from pre-ratification industry coverage (JEDEC JC-42.3 draft status, LPDDR6/JESD209-6 published July 2025, vendor roadmap disclosures from Samsung/SK hynix/Micron/Intel/AMD/NVIDIA as reported through mid-2026) — verify against the final ratified JEDEC DDR6 specification once published.