DDR4

Memory Updated Sep 2026

DDR4 SDRAM

The fundamentals of DDR4 SDRAM architecture — voltage, prefetch, bank topology, on-die termination, clocking, and bus error handling.

!!! info "The basic DRAM cell"
DDR4 stores data the same way every DDR generation does: one transistor, one capacitor per bit, refreshed periodically because the capacitor leaks charge. Everything below describes the machinery built around that cell to get data in and out reliably at DDR4's operating speeds.

1. Overview

!!! abstract "Core specs"
Introduced 2014. Operates at 1.2 V. Data rates from 1600 to 3200 MT/s. Standard desktop DIMM uses 288 pins.

Feature	DDR4
Introduction	2014
Typical voltage	1.2 V
Data rates	1600–3200 MT/s
DIMM pins (desktop)	288
Prefetch / burst length	8n / BL8
Banks	16 in 4 bank groups
Channel width per DIMM	Single 64-bit channel
Signaling	POD12

CPU
  │
Memory Controller
  │
Address/Command Bus
  │
DRAM Chips

Inside the DRAM chip:

Rows
──────────────
[row]
      │
      ▼
Sense Amplifiers
      │
      ▼
Column Select
      │
      ▼
I/O Drivers

2. Bank Topology

!!! note "Why bank groups exist"
A single bank can only service one command at a time — after an activate, it needs time to recover (tRC) before it can be activated again. As burst length and prefetch width grew, a single bank couldn't be fed fast enough on its own.

DDR4 introduces 16 banks organized into 4 bank groups (4 banks per group). Bank grouping is the main architectural lever DDR4 pulls to improve effective throughput without simply raising clock speed: the controller can interleave accesses across different bank groups faster (tCCD_S) than repeated accesses to the same group (tCCD_L), so spreading traffic across groups keeps the data pipeline fuller than DDR3's flat 8-bank layout allowed.

DDR4 still uses a single 64-bit channel per DIMM — the subchannel split doesn't arrive until DDR5.

3. Package-Level Details

!!! info "Package vs. DIMM"
A DIMM is a board populated with several DRAM packages. The specs below describe the DRAM IC package itself — the FBGA chip soldered or reflowed onto the module.

Aspect	DDR4
Package type	78/96-ball FBGA, ~0.8 mm pitch
Max practical die density	16 Gb
Multi-die packaging	3DS with TSV (through-silicon via) stacking, up to 4–8 dies
Command pins	Encoded command bus
Added reliability pins	+ PAR (command/address parity), + ALERT#
Power delivery to package	From board VRM

Data width per chip (x4 / x8 / x16): x4 for high-capacity ECC/RDIMM setups, x8 for typical consumer DIMMs, x16 for low chip-count modules — the same convention every DDR generation follows.

DDR4's move to 3DS/TSV stacking (through-silicon vias connecting stacked dies directly, versus DDR3's wire-bonded dual-die packages) is what enables its higher practical density ceiling and is a foundational technique later generations build on further.

4. Power Delivery

DDR4 draws its operating voltage regulation from the motherboard VRM, the same model DDR3 used — there's no on-module power management in DDR4. A power-delivery fault remains a board-level issue, separately diagnosable from the memory module itself.

Motherboard VRM
      │
  DRAM Chips

5. On-Die Termination (ODT)

!!! abstract "Why termination exists"
At multi-gigatransfer speeds, data and command lines behave like transmission lines. An unterminated line reflects signal energy back from the open end of the trace, and that reflection corrupts the next bit. ODT is switchable resistance built into the DRAM die (and host controller) that absorbs the reflection.

DDR4 expands on ODT significantly compared to earlier generations. Each DQ/DQS pin — and now also the command/address pins — has a resistor network switchable between several values (commonly 240 Ω, 120 Ω, 60 Ω, sometimes 40 Ω), set via mode register commands.

ODT mode	Purpose
`RTT_NOM`	Default termination during normal (non-write) operation
`RTT_WR`	Termination applied specifically during writes to that rank
`RTT_PARK`	Termination for a rank that is idle but must stay "quiet" without reflection-causing high impedance

Key DDR4 additions:

Dynamic ODT — the termination value can switch mid-burst without issuing a new mode-register command, letting the controller adapt termination within a single transaction.
CA_ODT — termination extended to the command/address bus itself, not just the data pins.

6. DLL (Delay-Locked Loop) & Clocking

!!! abstract "Core idea"
The DLL phase-aligns the DRAM's internal DQ/DQS output timing with the external clock, compensating for propagation delay through the die's I/O circuitry. Without it, read data strobes drift out of phase with the clock as frequency increases and the controller can't reliably latch data.

DDR4 keeps the same core DLL concept as DDR3, active during normal operation and requiring relock (tDLLK) after exiting states like self-refresh. Two additions:

DLL-off mode — for low-power states where the DLL doesn't need to stay locked, improving idle power consumption versus DDR3's always-active DLL.
Geardown mode — reduces clocking overhead for the command/address bus as command timing grew more complex with the introduction of bank groups.

DDR4 also introduces write CRC and command/address parity (covered in §7) as part of the same generational push toward more on-die timing and error circuitry, though these are error-handling features rather than DLL functions themselves.

7. Bus Error Handling

DDR4 adds meaningful in-transit error protection that DDR3 lacked entirely, though it still has no on-die ECC and no read-path protection:

7.1 Write CRC (data bus, host → DRAM)

Controller computes a CRC over the write burst and sends it alongside the data.
DRAM independently computes its own CRC on what it received and compares.
Mismatch → DRAM asserts ALERT# low → controller retries the write (it still has the original data buffered).

7.2 Command/Address Parity

Every command/address transfer carries a parity bit. A parity violation also asserts ALERT#, and the controller re-issues the command. This matters more than a data error would — a corrupted address bit could activate the wrong row entirely.

7.3 What DDR4 still doesn't cover

No on-die ECC. The array itself has no internal parity computed and checked inside the chip — that arrives as a mandatory baseline in DDR5.
No read-path CRC. The read path (DRAM → controller) has no native error detection. Writes are protected because the controller can trivially retry — it still holds the data. Reads have no equivalent fallback.

7.4 Summary Table

Error location	Detection mechanism	Response
Write data on DQ bus	Write CRC	`ALERT#` asserted → controller retries write
Command/address bus	C/A parity	`ALERT#` asserted → controller retries command
DRAM array (storage)	None on-die	System-level ECC-DIMM only, if present
Read data on DQ bus	None	Silent corruption unless system-level ECC is present

System-level ECC (an ECC-capable DIMM with an extra 8-bit-wide data lane, 72 bits total instead of 64) remains optional in DDR4, exactly as in DDR3, and is the only mechanism protecting the array and the read path.

8. Bandwidth Reference

Assuming a single 64-bit channel:

Memory	Peak bandwidth
DDR4-1600	12.8 GB/s
DDR4-2400	19.2 GB/s
DDR4-2933	23.5 GB/s
DDR4-3200	25.6 GB/s

9. Study Checklist

[ ] Explain why capacitor leakage requires periodic row refresh
[ ] State DDR4's voltage, prefetch, and bank-group organization
[ ] Explain why bank groups exist and what tCCD_S vs tCCD_L means
[ ] Describe DDR4's 3DS/TSV stacking and how it differs from DDR3's DDP wire-bonding
[ ] Explain what RTT_NOM, RTT_WR, and RTT_PARK each control
[ ] Explain dynamic ODT and CA_ODT — what's new in DDR4 versus earlier ODT
[ ] Explain DLL-off mode and Geardown mode
[ ] Trace what happens when write CRC or C/A parity detects an error (ALERT# → retry)
[ ] Explain why DDR4 still has no on-die ECC and no read-path protection

References: DDR4 JEDEC specification (JESD79-4).