UART/RS232

General Engineering Updated Sep 2026

4. UART / RS232

Best for: Simple point-to-point communication between two devices (debugging consoles, simple modems).

How it works: Asynchronous protocol using just two wires: Transmit (TX) and Receive (RX). It does not use a clock line, meaning both devices must agree on a set speed (baud rate) beforehand. RS232 is the higher-voltage, longer-distance version of standard logic-level UART.

Speed: Usually 115.2 kbps, but can go up to a few Mbps.

Distance: Up to 15 meters for RS232; centimetres for logic-level UART.

UART and RS232 Technical Reference Guide

This document provides a comprehensive technical overview of the physical layer, packet structure, flow control, and error handling mechanisms of the UART interface, alongside an architectural breakdown of RS232 compatibility.

1. UART Physical Connection

The UART (Universal Asynchronous Receiver-Transmitter) interface is a point-to-point, asynchronous communication protocol. Unlike synchronous interfaces (such as I2C or SPI), UART does not utilize a shared clock line to synchronize data bits. Instead, it relies on pre-configured hardware timing settings (baud rates) programmed identically on both devices.

A standard full-duplex UART connection requires exactly two data wires plus a shared ground line:

TX (Transmit Data): The line used by a device to send data to the remote receiver.
RX (Receive Data): The line used by a device to accept incoming data from the remote transmitter.

[ Device A (UART) ]                   [ Device B (UART) ]
  * TX  ------------------------------------>  RX *
  * RX  <------------------------------------  TX *
  * GND ------------------------------------> GND *

Push-Pull Architecture

Standard UART pins operate on a push-pull configuration at logic-level voltages (commonly referred to as TTL/CMOS logic, typically 1.8V, 3.3V, or 5V):

The transmitter actively drives the line high to represent a logic 1 (Idle/Mark).
The transmitter actively drives the line low to represent a logic 0 (Space).
Because the line is actively driven in both directions, it cannot be shared among multiple transmitters without creating a short circuit. This restricts standard UART strictly to point-to-point topologies.

2. Packet Structure and Data Transfer

Because there is no clock line, the receiver must constantly monitor the RX line for state changes. Communication is broken down into individual data frames.

Frame Conditions

Idle State (Mark): When no data is being transmitted, the line remains continuously driven high (1).
Start Bit: To initiate a transfer, the transmitter pulls the line low (0) for exactly one bit period. This alerts the receiver's internal timer to begin sampling incoming data.
Stop Bit: After data transmission is complete, the transmitter drives the line high (1) for 1, 1.5, or 2 bit periods to mark the end of the frame and reset the line to the idle state.

Packet Flow

A standard UART data frame consists of a Start Bit, 5 to 9 Data Bits, an optional Parity Bit, and 1 or more Stop Bits. The most common configuration in the industry is 8N1 (8 Data bits, No parity, 1 Stop bit).

 [ IDLE (1) ] -> [ START BIT (0) ] -> [ 5 to 9 DATA BITS (LSB First) ] -> [ PARITY BIT (Optional) ] -> [ STOP BIT (1) ]

Bit Sampling: Upon detecting the falling edge of the Start Bit, the receiver waits 1.5 bit periods so it can sample the first actual data bit precisely in the middle of its timing window. It then samples subsequent bits exactly 1 bit period apart to avoid edge jitter.
Bit Order: Data bits are transmitted LSB (Least Significant Bit) first and completed with the MSB (Most Significant Bit).

3. UART/RS232 Oscilloscope Timing Diagram

The visual representation below shows how the hardware lines interact during a standard 8N1 transmission of the ASCII character 'A' (Hexadecimal 0x41, Binary 01000001).

Because UART sends data LSB first, the binary sequence on the wire appears reversed: 1, 0, 0, 0, 0, 0, 1, 0.

       IDLE   START  D0(LSB)  D1     D2     D3     D4     D5     D6    D7(MSB)  STOP   IDLE
Logic   (1)    (0)     (1)    (0)    (0)    (0)    (0)    (0)    (1)     (0)    (1)     (1)
       ______        _______                                   _______        _______________
TTL/   :     \______/       \_________________________________/       \______/     :         :
CMOS   :     :      :       :                                 :       :      :     :         :
       :     :      :       :                                 :       :      :     :         :
       :     :      _______ :                                 _______ :      :____ :         :
RS232  :____/      /       \_________________________________/       \______/     \_________:
Voltages(Low):     :(High)  :                                 :(High) : (Low):     :(Low)    :
       :     :      :       :                                 :       :      :     :         :
       :<--->:<--->:<------>:<------>:<------>:<------>:<------>:<------>:<------>:<--->:         :

             |      |                                                        |     |
         Trigger  Sample                                                   Sample  Reset
         Falling   Bit 0                                                    Bit 7  Line
          Edge

Key Oscilloscope Identification Markers

The Start Trigger: Set your oscilloscope to trigger on a negative/falling edge. The transition from the high idle rail to the low ground rail marks the start bit.
Baud Rate Measurement: Measure the horizontal distance (time delta Δ t) of the shortest single bit pulse. The inverse of this value determines your baud rate (Baud = 1 / Δ t). For example, a 104.16 μs bit width signifies 9600 baud.
Voltage Inversion Check: Always verify whether you are probing logic-level TTL or true RS232 hardware. As seen above, RS232 physically inverts the signal profile relative to standard logic levels.

4. Flow Control, Error Detection, and Correction

Flow Control Mechanisms

To prevent a fast transmitter from overflowing a slower receiver’s internal hardware buffer, UART utilizes two distinct flow control methods.

1. Hardware Flow Control (RTS/CTS)

This method adds two physical hardware wires to the interface bus:

RTS (Request to Send): Driven by the receiver to inform the transmitter that it is ready to receive data.
CTS (Clear to Send): Monitored by the transmitter. The transmitter will only dump data onto the TX line if it senses that the receiver has asserted the CTS line.

2. Software Flow Control (XON/XOFF)

This method requires no extra hardware lines, utilizing the standard RX/TX data lines to send specialized control characters directly inside the data stream:

XOFF (0x13): The receiver transmits this byte to command the remote device to pause transmission immediately.
XON (0x11): Sent by the receiver once its buffer clears, signaling the remote device that it is safe to resume.
Note: Software flow control can corrupt binary data file transfers if the raw file payload naturally contains the bytes 0x11 or 0x13.

Error Detection Mechanisms

UART does not feature hardware-level error correction. It relies on three low-level hardware status flags to detect corrupted framing:

Parity Error: If parity checking is enabled (Even or Odd), the transmitter counts the number of 1 bits in the payload and sets an extra bit to make the total number of 1 bits consistently even or odd. If the receiver computes a different tally, a parity error flag is raised.
Framing Error: Occurs when the receiver samples the bus at the designated position for the Stop Bit, but finds the line pulled low (0) instead of resting high (1). This typically implies mismatched baud rates between the devices.
Overrun Error: Triggered when a new data frame arrives completely and overwrites the hardware receive register before the system CPU has finished reading the previous byte out of it.

5. RS232 Compatibility Breakdown

UART defines the internal protocol layout (the start, data, and stop bits), while RS232 defines the external physical and electrical characteristics of the wiring network. You cannot connect a microcontroller's UART pins directly to an RS232 serial port without using an intermediate level-shifter integrated circuit (e.g., a MAX232 chip) to convert the incompatible voltage levels.

Feature	Logic-Level UART (TTL/CMOS)	RS232 Standard
Signal Type	Single-Ended (referenced to GND)	Single-Ended (referenced to GND)
Logic Low (`0` / Space)	0 V (GND)	+3 V to +15 V
Logic High (`1` / Mark)	1.8 V, 3.3 V, or 5 V	-3 V to -15 V
Undefined Dead-Zone	Between 0.8 V and 2.0 V	-3 V to +3 V
Typical Distance Max	< 1 meter	15 meters (50 feet)
Standard Connector	PCB Headers / Solder Pads	DB9 or DB25 Pins
Common Application	Inter-chip MCU communication	Industrial machinery, legacy modems

Key Architectural Differences

Electrical Voltage Inversion: Logic levels are completely inverted. In standard UART, high voltage represents a logic 1. In RS232, a logic 1 (Mark) is represented by a negative voltage between -3V and -15V. A logic 0 (Space) is represented by a positive voltage between +3V and +15V.
Noise Immunity and Distance: Standard microcontroller UART lines are highly susceptible to electromagnetic interference (EMI) and line capacitance over distances greater than a few centimeters. RS232 utilizes wide voltage swings (up to a 30V absolute differential peak-to-peak swing), allowing it to cut through industrial environmental noise and push across cables up to 15 meters long.
The Bipolar Threshold Zone: RS232 receivers incorporate an intentional hardware dead-zone between -3V and +3V. Any voltage floating within this window is ignored as noise, preventing minor electrical hums from falsely triggering false start bits.

6. References

Analog Devices: Fundamentals of RS-232 Serial Communications

Comprehensive engineering baseline covering terminal configurations, signal definitions, and modem interaction rules.DigiKey Standard Repository: Understanding the RS-232 Standard
Hardware baseline architecture explaining voltage inversion scales and industrial serial bus physics.EIA-232 Standard Family Documentation (TIA/EIA-232-F)
The original defining document series governed by the Electronic Industries Alliance covering standard pinning and signal criteria.