Intro to RTL Design for ASICs

Engineering notebook entry — plain-language primer, not a reference.

1. What "RTL" Means

RTL stands for Register-Transfer Level. It's a way of describing digital hardware as:

• Registers — storage elements (flip-flops) that hold state between clock edges
• Transfers — the combinational logic that computes new values to move into those registers on the next clock edge

Instead of drawing individual transistors or gates, you write code (usually Verilog, SystemVerilog, or VHDL) that describes what data moves where, and under what conditions, on every clock cycle. A synthesis tool later turns that description into actual gates for a target process node.

RTL sits in the middle of the abstraction stack:

Architecture / spec  (what the chip should do)
        │
        ▼
   RTL design        ← you are here
        │
        ▼
   Gate-level netlist (synthesis)
        │
        ▼
   Physical layout    (place & route)
        │
        ▼
   Fabricated silicon

2. Combinational vs. Sequential Logic

Every RTL design is built from two kinds of logic:

Type	Behavior	Verilog construct
Combinational	Output depends only on current inputs, no memory	assign, or always @(*)
Sequential	Output depends on current inputs and stored state, updates on a clock edge	always @(posedge clk)

A simple example of each:

// Combinational: a 2-input AND gate
assign y = a & b;

// Sequential: a D flip-flop
always @(posedge clk) begin
    q <= d;
end

Almost all real RTL is some mix: combinational logic computes a "next state," and a clocked register captures it.

3. The Classic Building Block: FSM + Datapath

Most non-trivial RTL blocks are organized as a finite state machine (FSM) controlling a datapath:

• Datapath — the registers, adders, muxes, and other elements that actually process data
• Controller (FSM) — sequential logic that decides, cycle by cycle, which datapath operations happen and when

A common coding style splits an FSM into two always blocks:

// State register (sequential)
always @(posedge clk or posedge rst) begin
    if (rst) state <= IDLE;
    else     state <= next_state;
end

// Next-state logic (combinational)
always @(*) begin
    case (state)
        IDLE:  next_state = start ? RUN : IDLE;
        RUN:   next_state = done  ? DONE : RUN;
        DONE:  next_state = IDLE;
        default: next_state = IDLE;
    endcase
end

This separation of "what state am I in" (sequential) from "what should I do next" (combinational) is one of the most reused patterns in RTL design.

4. Clocking and Reset

Two things every block needs to get right, because they're the source of most real bugs:

• Clock domain — what clock does this logic run on? Mixing signals from two different clocks without proper synchronization (e.g., a 2-flop synchronizer) causes metastability bugs that are notoriously hard to debug.
• Reset strategy — synchronous vs. asynchronous reset is a real design decision, not a detail. Asynchronous resets react immediately but can cause reset-release timing issues; synchronous resets are cleaner for timing closure but need the clock running to take effect.

5. Why RTL Style Matters

The code you write isn't just documentation — it's literally translated into gates by the synthesis tool. A few habits that matter in practice:

• Avoid latches unless intentional. An incomplete if/case in combinational logic (missing an else or default) implies memory the synthesis tool will build as a latch — usually not what you wanted.
• One clock per always block. Don't mix logic driven by different clock edges in the same sequential block.
• Non-blocking (<=) for sequential, blocking (=) for combinational. Mixing these up is a classic source of simulation-vs-synthesis mismatches.
• Keep control and datapath separate where possible. Makes the design easier to verify and reuse.

6. From RTL to Silicon (High-Level Flow)

1. RTL design — write the Verilog/VHDL description
2. Functional verification — simulate against a testbench to confirm behavior matches the spec, before spending time on synthesis
3. Synthesis — a tool (e.g., Synopsys Design Compiler, Cadence Genus) maps RTL to a gate-level netlist in a target standard-cell library, optimizing for timing/area/power
4. Physical design — place & route, clock tree synthesis, timing closure
5. Sign-off — static timing analysis, DRC/LVS, power analysis
6. Tapeout — the design is sent to the foundry

RTL design is only step 1, but decisions made here — pipelining, clocking scheme, reset strategy, how much state is exposed — largely determine how easy or painful every later step will be.

7. Quick Glossary

Term	Meaning
RTL	Register-Transfer Level
FSM	Finite State Machine
Synthesis	Translating RTL into a gate-level netlist
Testbench	Code that drives inputs and checks outputs to verify RTL behavior
Metastability	An unpredictable, unresolved logic state caused by violating timing at a flip-flop input, common at clock domain crossings
STA	Static Timing Analysis — verifying timing without simulation
DRC / LVS	Design Rule Check / Layout Versus Schematic — physical design sign-off checks

Further Reading

• IEEE 1364 (Verilog) / IEEE 1800 (SystemVerilog) language standards
• Any standard "Digital Design" textbook (e.g., Harris & Harris, Digital Design and Computer Architecture) for the underlying logic design fundamentals