I2C

General Engineering Updated Sep 2026

I2C (Inter-Integrated Circuit)

Best for: On-board, short-distance chip-to-chip communication (sensors, displays, EEPROMs).

How it works: Uses two bidirectional, open-drain lines: Serial Data (SDA) and Serial Clock (SCL). It employs a master-slave architecture where the master controls the clock and targets specific device addresses.

Speed: 100 kbps (Standard), 400 kbps (Fast), up to 3.4 Mbps (High-speed).

Distance: Very short, typically under 1 meter.

I2C and SMBus Technical Reference Guide

This document provides a comprehensive technical overview of the physical layer, packet structure, flow control, and error handling mechanisms of the I2C interface, alongside an architectural breakdown of SMBus compatibility.

1. I2C Physical Connection

The I2C (Inter-Integrated Circuit) interface uses a synchronous, multi-master/multi-slave configuration requiring exactly two wires plus a shared ground line:

SDA (Serial Data): The bidirectional line used to transmit data bits.
SCL (Serial Clock): The line carrying the clock pulses generated by the active master to synchronize data transfer.

Open-Drain Architecture

Both lines utilize an open-drain (or open-collector) hardware configuration:

Devices can only pull the lines low (to ground).
Devices cannot actively drive the lines high.
Pull-up resistors (typically 2 kΩ to 10 kΩ) must connect each line to the supply voltage ((V_{CC})) to pull them high when the bus is idle.
This design prevents short circuits and hardware damage if two devices attempt to drive the bus simultaneously.

2. Packet Structure and Data Transfer

Data transmission follows a strict sequential protocol. Changes on the SDA line must only occur when SCL is low. If SDA changes while SCL is high, it signals a control condition (Start or Stop).

Frame Conditions

Start Condition (S): The master pulls SDA low while SCL remains high. This alerts all slave devices that a transmission is beginning.
Stop Condition (P): The master releases SDA from low to high while SCL remains high. This frees up the bus.

Packet Flow

Every packet sent over the bus is exactly 8 bits (1 byte) long, followed by a 9th bit for acknowledgment.

 [ START ] -> [ 7-Bit Address ] -> [ R/W Bit ] -> [ ACK/NACK ] -> [ 8-Bit Data Byte ] -> [ ACK/NACK ] -> [ STOP ]

Address Frame: The master issues a Start Condition, then broadcasts a 7-bit slave address.
Read/Write Bit: The 8th bit of the address frame specifies the operation direction. 0 indicates a Write; 1 indicates a Read.
Data Frame: The master or slave (depending on the R/W bit) transmits 8 bits of data, MSB (Most Significant Bit) first.

3. I2C Oscilloscope Timing Diagram

The visual representation below shows how the hardware lines interact during a standard Write operation (7-bit address 0x2D, writing data byte 0x41).

Notice that SDA only changes when SCL is low, except during the Start and Stop conditions.

       START                                                                   STOP
SCL ____     ___   ___   ___   ___   ___   ___   ___   ___   ___   ___         ____
        \___/   \_/   \_/   \_/   \_/   \_/   \_/   \_/   \_/   \_/   \_______/
Bit       S    A6    A5    A4    A3    A2    A1    A0   R/W   ACK   D7 ... D0   P

          |    (0)   (1)   (0)   (1)   (1)   (0)   (1)   (0)   (0)  (01000001)  |
SDA __       _______           ___________                 ___   ___       ______
      \_____/       \_________/           \_______________/   \_/   \_____/
             <------------- ADDRESS (0x2D) -------------> | Write| Master |<- DATA ->| Master

                                                                 | Releas | (0x41)   | Releas
                                                                 | Slave  |          |
                                                                 | Pulls  |          |
                                                                 | Low    |          |

Key Oscilloscope Identification Markers

The Start Trigger: Look for the falling edge of SDA while SCL is still resting at a steady high voltage state.
The Clock Line (SCL): A continuous series of square waves generated exclusively by the master device.
Data Validity Window: Center your oscilloscope cursor in the middle of the high pulse of SCL to read the stable state of the SDA line.
The Handshake (ACK): On the 9th clock pulse, you will often see a slight voltage dip or step if the slave device has a slightly different ground potential than the master, confirming the slave is pulling the line down.

4. Flow Control, Error Detection, and Correction

Clock Stretching (Flow Control)

I2C manages data pacing through a hardware-level mechanism called Clock Stretching:

A slave device might receive data faster than it can process it (e.g., writing to internal EEPROM).
To pause the master, the slave holds the SCL line low after an acknowledgment bit.
The master attempts to release SCL to high for the next bit, but detects that the line is still low. The master pauses its internal clock and waits until the slave releases SCL before resuming transmission.

ACK/NACK Mechanism

Standard I2C has no native error correction and relies on a basic hardware detection mechanism. After every 8-bit byte, the transmitting device releases the SDA line. The receiving device must pull SDA low during the 9th clock pulse to issue an ACK (Acknowledge). If the line stays high, it is a NACK (Not Acknowledge). A NACK indicates:

The targeted slave device is not present on the bus.
The slave is busy or unable to understand the data.
The receiver has run out of data to send (during a read operation).

Bus Arbitration and Collision Avoidance

When multiple masters attempt to control the bus at the same time, a hardware arbitration protocol prevents data corruption:

Masters continuously monitor the SDA line while transmitting.
If Master A tries to send a "high" bit (by releasing SDA), but Master B sends a "low" bit (pulling SDA down), Master A will detect that the line is low.
Master A immediately loses arbitration, shuts off its data drivers, and waits for a Stop condition. Master B continues its transmission uninterrupted without losing a single bit.

5. SMBus Compatibility Breakdown

While SMBus (System Management Bus) is fundamentally derived from I2C, they are not completely identical. You can connect I2C and SMBus devices together, but you must account for differences in timing, voltage thresholds, and timeout behavior.

Feature	Standard I2C	SMBus
Minimum Clock Speed	DC (0 Hz)	10 kHz
Bus Timeout	None (Can hang indefinitely)	35 ms (Strict reset limit)
Logic Low Level ($V_{IL}$)	$0.3 \times V_{CC}$ (Variable)	Fixed at 0.8 V max
Logic High Level ($V_{IH}$)	$0.7 \times V_{CC}$ (Variable)	Fixed at 2.1 V min
Max Sink Current	3.0 mA	350 µA
Hardware Interrupt Line	No (Requires master polling)	Yes (`SMBALERT#`)
Built-in Error Checking	No	Yes (Packet Error Checking / CRC-8)

Key Architectural Differences

Clock Speed and Timeout Lockups: I2C allows a slave to hold SCL low indefinitely. SMBus introduces a 35 millisecond timeout constraint. If a slave holds SCL low for longer than 35 ms, all devices must reset their interface logic and release the bus to prevent system lockups.
Electrical Voltage Thresholds: I2C uses $V_{CC}$-dependent logic levels (e.g., a 5V I2C device requires 3.5V to register a high state). SMBus uses fixed electrical thresholds ($V_{IL} = 0.8\text{V}$, $V_{IH} = 2.1\text{V}$), allowing it to bridge systems running on different voltage rails (like 1.8V, 3.3V, and 5V) without level shifters.
Current and Pull-Up Drive: SMBus defines a maximum sink current of 350 µA, using pull-ups paired with a constant current source to precisely control rise times. I2C allows sink currents up to 3 mA, which accommodates lower-value pull-up resistors to drive long, highly capacitive bus lines at faster speeds.
The Extra Hardware Line (SMBALERT#): Instead of forcing the master to periodically poll slave chips (wasting CPU overhead), SMBus introduces an optional third wire called SMBALERT#. When a slave pulls this shared open-drain line low, the master issues a read command to a universal Alert Response Address (0x0C). The asserting slave replies with its unique address, notifying the master instantly.
Packet Error Checking (PEC): SMBus incorporates a robust CRC-8 error check appended to the end of data packets to catch corrupt bits caused by environmental noise. Standard I2C devices view this extra byte as an unneeded data frame and will throw an unexpected data error unless manually handled in your software drivers.