NAND

Storage / SSD Updated Sep 2026

NAND Flash Overview (for SSDs)

A high-level reference on NAND flash memory as used in SSDs — cell types, physical structure, program/erase behavior, and how it ties into the bottleneck model and form-factor notes elsewhere in this notebook. This is a conceptual/reference doc, not a specific-drive datasheet; numbers below are industry-typical ranges as of 2026 and should be cross-checked against a target device's datasheet for real analysis.

1. What NAND Flash Is

NAND flash is non-volatile memory that stores bits as trapped electric charge in an array of floating-gate or charge-trap transistors, organized so that entire pages are programmed/read together and entire blocks are erased together (as opposed to NOR flash, which is randomly addressable like RAM but slower to write and lower density). It's called "NAND" because the cells within a string are wired in series, resembling a NAND logic gate — this series wiring is what makes NAND dense and cheap per bit, at the cost of only being usable in page/block-sized operations rather than arbitrary byte-level access.

In an SSD, NAND is the persistent storage medium sitting behind the controller, DRAM (if present), and NAND flash interface — see ssd-controller-architecture §5–8 for how NAND's physical limits translate into throughput/IOPS ceilings.

2. Cell Types — Bits per Cell

The number of distinct voltage levels a cell must reliably distinguish is what trades off density against endurance, retention, and speed.

Type Bits/cell Voltage states P/E cycle endurance (typical) Data retention (typical, at end of life) Relative cost/GB Typical SSD use
SLC 1 2 ~50,000–100,000 10+ years Highest Enterprise write-cache tiers, industrial/embedded, pSLC cache regions
MLC 2 4 ~3,000–10,000 5–10 years High Legacy enterprise/prosumer drives
TLC 3 8 ~1,000–3,000 3–5 years Moderate Mainstream client and enterprise SSDs (dominant today)
QLC 4 16 ~100–1,000 1–3 years Low Capacity/read-heavy enterprise, high-capacity client
PLC 5 32 <100 (emerging, not yet mainstream) <1 year Lowest (target) Cold/archival tiers — still largely in development

Notes:

  • Endurance and retention are inversely coupled to density: more voltage levels packed into the same cell means smaller margins between states, more sensitive sensing, and faster wear per program/erase (P/E) cycle.
  • Nearly all modern SSDs — including QLC drives — use a pseudo-SLC (pSLC) write cache, where a portion of the TLC/QLC array is temporarily operated in 1-bit-per-cell mode for speed and endurance, then folded to native density in the background. See ssd-controller-architecture §7 for the burst-vs-sustained throughput implications.
  • These P/E cycle and retention numbers vary significantly by vendor, node, and how conservatively the FTL manages wear — treat them as order-of-magnitude, not spec-grade.

3. Storage Mechanism: Floating Gate vs. Charge Trap

Aspect Floating Gate (FG) Charge Trap (CTF)
Storage layer Conductive polysilicon "floating" gate Insulating nitride trapping layer
Charge behavior Charge spreads freely across the conductor Charge stays localized where it was injected
Defect tolerance A single oxide defect can drain the whole gate A local defect only drains charge near that spot — more robust
Tunnel oxide Must be thicker to prevent charge leakage Can be thinner, enabling faster program/erase
Manufacturing in 3D stacks Requires the gate to be patterned/isolated per layer — hard to scale vertically Nonconductive layer needs no per-cell isolation — much easier to stack vertically

Modern 3D NAND overwhelmingly uses charge-trap architecture specifically because it doesn't need to be etched/isolated in the vertical direction, which is what makes deep vertical stacking (100s of layers) manufacturable. Planar (2D) NAND, now essentially legacy, was predominantly floating-gate.

4. 2D (Planar) vs. 3D NAND

Planar NAND scaled density purely by shrinking the lithography node, but below roughly the 15–19nm range, cells became too close together for reliable charge isolation (cell-to-cell interference, reduced endurance/retention). 3D NAND solved this by stacking cells vertically in layers instead of shrinking them further laterally — trading lithographic scaling for layer-count scaling, which has proven to have a much longer runway.

Today, essentially all SSD NAND is 3D (also called V-NAND, BiCS, or similar vendor names). Layer count is now the primary density lever, alongside bits/cell.

5. Physical/Logical Hierarchy

Package (physical chip, 1+ dies, shares a CE# pin per die or stacked dies)
 └─ Die (smallest independently-operable unit; has its own I/O queue)
     └─ Plane (subdivision of a die; multiple planes can execute ops concurrently)
         └─ Block (the ERASE unit)
             └─ Page (the PROGRAM/READ unit)
                 └─ Cell (the physical transistor; stores 1–5 bits depending on type)
Level Typical size (modern 3D TLC/QLC) Operation granularity
Page ~16 KB (data) + spare/ECC area Program (write), Read
Block ~4–8 MB (hundreds of pages per block) Erase
Plane Multiple blocks; 2–4 planes/die common Concurrent program/read/erase across planes
Die Multiple planes; independent command queue Concurrent ops across dies on a channel
Package 1 or more dies (often stacked, sharing a channel) —

This hierarchy is the physical basis for the parallelism terms (Planes x Dies_per_channel x N_channels) used in ssd-controller-architecture §6.

6. Program / Erase / Read Operations

The core asymmetry that shapes almost everything about SSD design: programs and reads happen at the page level, but erases happen at the block level, and a page cannot be reprogrammed in place without an intervening block erase.

Operation Granularity Relative latency Notes
Read (t_R) Page Fastest (~tens of µs) Non-destructive
Program/Write (t_PROG) Page Slower than read (~hundreds of µs to ~1-2 ms, density-dependent) Can only write to an erased page; SLC mode is fastest, QLC native mode slowest
Erase (t_BERS) Block Slowest (~a few ms to ~10+ ms) Wipes an entire block; amortized cost per page is what matters for sustained throughput

Because pages can't be overwritten in place, the FTL (flash translation layer) always writes to pre-erased pages and marks old versions invalid, relying on garbage collection to reclaim blocks — this is the origin of write amplification (WAF), covered in ssd-controller-architecture §8.

7. Multi-Bit Cell Page Structure

For MLC/TLC/QLC cells, each physical cell encodes multiple bits, and those bits are distributed across multiple logical pages that share the same physical cell array — commonly called the lower, middle, and upper page (and beyond, for QLC/PLC). Practical implications:

  • Programming a TLC/QLC cell to its final state generally requires multiple programming passes across the associated logical pages, which is part of why native TLC/QLC t_PROG is slower than SLC t_PROG.
  • Reliability differs by page: upper pages (encoding the finest voltage distinctions) are typically more error-prone than lower pages, influencing how the ECC engine allocates parity/error-correction strength.
  • This is the underlying reason pSLC caching helps so much — writing in SLC mode uses only one logical page per cell with the widest possible voltage margins, avoiding the slow multi-pass native programming entirely.

8. NAND Flash Interfaces: Toggle Mode vs. ONFI

The electrical/protocol interface between the controller and the NAND package is standardized under two competing (but functionally similar) specs:

Interface Backed by Typical top speed (2026-era) Notes
Toggle Mode (DDR) Samsung, SK hynix, Kioxia/WD Toggle DDR5-class parts around ~3600+ MT/s Widely used by the Samsung/SK hynix/Kioxia camp
ONFI (Open NAND Flash Interface) Micron, Intel (historical), others ONFI 5.x-class parts in a similar multi-GT/s range JEDEC-adjacent open standard, JESD230

Both interfaces define the per-channel bus that feeds into BW_channel_total = InterfaceClock x BusWidth x N_channels in the bottleneck model (ssd-controller-architecture §5) — this is a hard ceiling on NAND-side bandwidth independent of how fast the NAND array itself can program/read.

9. Error Mechanisms & Wear

Mechanism Cause Effect
Read disturb Repeatedly reading a page slightly stresses unselected cells on the same block Bit errors accumulate in neighboring, unread pages over many reads
Program disturb Voltage applied to program one page slightly affects adjacent cells Bit errors in nearby pages/cells
Retention loss Trapped charge slowly leaks over time, faster at high temperature or after heavy wear Raw bit error rate (RBER) rises the longer data sits unrefreshed, especially near end-of-life
Wordline/cell-to-cell coupling Denser layers and finer voltage margins (TLC/QLC/PLC) increase sensitivity to neighboring cell state Higher baseline RBER at higher bits/cell
Cumulative wear (P/E cycling) Each program/erase cycle stresses the tunnel oxide Endurance limit — RBER rises and speed can degrade as a block approaches its rated P/E cycle count

All of these are why ECC/LDPC engines exist and get stronger (more parity, more read-retry steps) as density increases — see ssd-controller-architecture §4, where BW_ECC must exceed raw NAND throughput at the required bit error rate, and degrades as more read-retry/decode iterations are needed near end-of-life.

10. Current-Generation Snapshot (2026)

Layer count is the primary density lever in 3D NAND today, alongside bits/cell. Roughly, as of mid-2026:

Vendor Current-gen layers (shipping ~2025-26) Next-gen target
Samsung V9T, 286 layers V10T, 400+ layers (2026 H1)
SK hynix V9T, 321 layers V10T, ~500 layers (targeted 2027)
Micron B68S, 276 layers B78, 300+ layers (targeted 2027)
Kioxia/WD BiCS 8, 218–232 layers BiCS 9T, 300+ layers (targeted 2027 H1)

Beyond simple layer-count increases, vendors are increasingly relying on string stacking (bonding multiple shorter NAND "decks" on top of each other) and hybrid bonding (bonding the memory array wafer directly to a separately-fabricated CMOS logic wafer) to keep scaling past what a single etched stack can achieve — Samsung has publicly discussed roadmaps toward 900+ layers using these techniques.

11. Where NAND Fits in the SSD

NAND is one link in the pipeline modeled in ssd-controller-architecture: host interface → controller/FTL → DRAM (mapping table) → ECC engine → NAND channel interface → NAND media array → (SLC cache burst/sustained behavior) → GC/WAF-bound sustained throughput. Physically, the NAND packages themselves are what occupy the board-area "NAND placements" left blank per form factor in form-factors — how many packages fit, and how many dies are stacked per package, is a per-drive PCB/thermal design choice constrained by the form factor's footprint and power budget.

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