DDR6

Memory Updated Sep 2026

DDR6 SDRAM (Draft / Pre-Ratification)

The fundamentals of DDR6 SDRAM as currently drafted — voltage, prefetch, channel topology, package, and bus error handling, to the extent any of this is publicly settled.

!!! warning "This is a draft standard — read this before anything else"
As of this writing, JEDEC has published the mobile companion spec, LPDDR6 (JESD209-6), in July 2025 — the first DDR6-era standard to actually ship. The desktop/server DDR6 specification itself is still in platform validation with Intel, AMD, NVIDIA, and the major DRAM manufacturers (Samsung, SK hynix, Micron). Numbers below are drawn from pre-ratification industry coverage and vary across sources — most notably the exact subchannel width and final operating voltage. Every figure on this page is directional, not authoritative. Verify against the ratified JEDEC spec before using any of this in real design work.

1. Overview

!!! abstract "Core specs (draft)"
Draft specification circulated by JEDEC in late 2024; still finalizing. Voltage is expected to be further reduced versus DDR5's 1.1 V, exact figure not yet settled. Base data rates target 8,800 to 17,600 MT/s, with overclocked/specialty grades reportedly aiming beyond 21,000 MT/s. Timeline consensus across industry coverage points to server/enterprise availability around 2026 and broader consumer availability in 2027–2028.

Feature	DDR6 (draft)
Status	Draft — JEDEC JC-42.3 subcommittee, not yet ratified as of this writing
Typical voltage	Further reduced vs. DDR5's 1.1 V — exact figure not finalized
Data rates	8,800–17,600 MT/s base roadmap; OC grades reportedly targeting 21,000+ MT/s
Physical form factor	New connector, not backward compatible with DDR5; CAMM2 favored for client/compact systems, server format still finalizing
Prefetch / burst length	Expected to extend beyond DDR5's BL16 — not yet published
Banks	Further bank-group increase expected to feed the wider prefetch — count not yet published
Channel width per DIMM	Reported as four subchannels per DIMM; per-subchannel width cited inconsistently (16-bit vs. 24-bit) across sources
Signaling	POD-based continuation expected; some vendor discussion of multi-level signaling, not JEDEC-confirmed

CPU
  │
Memory Controller
  │
Address/Command Bus
  │
DRAM Chips

The underlying cell-level pipeline is expected to remain conceptually unchanged from every prior DDR generation:

Rows
──────────────
[row]
      │
      ▼
Sense Amplifiers
      │
      ▼
Column Select
      │
      ▼
I/O Drivers

2. Channel Topology (Draft)

DDR6 drafts describe a four-subchannel-per-DIMM structure — each subchannel with its own command/address bus, the same basic idea DDR5 introduced with its two-subchannel split, extended further:

DDR6 DIMM (draft)
~16–24-bit channel
~16–24-bit channel
~16–24-bit channel
~16–24-bit channel

!!! warning "Why the per-subchannel width is shown as a range"
Pre-ratification coverage describes the subchannel split inconsistently — some sources say four 16-bit subchannels, others four 24-bit subchannels. The direction (more, narrower subchannels than DDR5) is consistent across sources; the exact width isn't publicly settled. This is a genuine open point in the draft, not an oversight in reporting.

The purpose of the further split is the same logic that motivated DDR5's two-way split: more independent subchannels means more outstanding operations a single physical module can service simultaneously, which matters most for small, random-access-heavy workloads (AI/ML inference, dense multi-core access patterns) rather than long sequential streams.

Bank and bank-group counts for DDR6 have not been published in the sources surveyed for this page. Given every prior generation increased bank-group count specifically to keep a wider prefetch fed, and DDR6's data rate roughly doubles DDR5's again, a further increase is a reasonable expectation — but treat it as inference, not a confirmed spec detail.

3. Package-Level Details (Draft)

!!! info "Package vs. DIMM"
A DIMM is a board populated with several DRAM packages. The specs below describe the DRAM IC package itself — the FBGA chip soldered or reflowed onto the module.

Aspect	DDR6 (draft)
Package type	Ball count/pitch not yet published; new package expected to support 4-subchannel routing
Max practical die density	Roadmap target up to 128 Gb per die
Multi-die packaging	3DS/TSV stacking expected to remain the primary path to the higher module capacities the density roadmap implies
Command pins	Further encoding/reduction expected — exact scheme not yet published
Added reliability	Continuation of on-die ECC baseline expected; LPDDR6 (the closest already-ratified relative) documents enhanced reliability/security features
Power delivery to package	Expected to continue DDR5's on-module PMIC model, likely with more regulation channels for four subchannels — exact topology not yet published

The density story is the headline package-level change. DDR5 tops out around 24–32 Gb per die in practical production. DDR6's roadmap target of up to 128 Gb per die is the reason forecasts mention 64 GB+ consumer sticks and 256 GB+ server modules — this is a capacity jump riding on the same die-stacking (3DS/TSV) trend already established in earlier generations, not a new packaging technique.

4. Power Delivery (Draft)

DDR5 moved voltage regulation onto the module itself via an on-DIMM PMIC. DDR6 drafts are expected to carry this model forward rather than reverse it, likely needing more regulation channels to serve a four-subchannel structure — though the exact PMIC topology hasn't been published.

Motherboard
      │
   5V Input
      │
  PMIC on DIMM (expected to continue)
      │
  DRAM Chips

The failure-domain trade-off DDR5 introduced — a dead PMIC takes the whole module down, versus a separately-diagnosable board-level VRM fault — is expected to persist unchanged into DDR6.

5. On-Die Termination (Draft)

!!! abstract "Why termination exists"
At multi-gigatransfer speeds, data and command lines behave like transmission lines. An unterminated line reflects signal energy back from the open end of the trace, and that reflection corrupts the next bit. ODT is switchable resistance built into the DRAM die (and host controller) that absorbs the reflection.

At DDR6's target speeds (8,800–17,600 MT/s), impedance tolerances tighten considerably further than DDR5's already-tight tolerances. The expected trajectory is for termination control to push down to the per-subchannel level of DDR6's four-way split, following the same pattern DDR5 established relative to DDR4 — but specific RTT values and termination modes have not been published as of this writing.

6. Clocking (Draft)

!!! abstract "Core idea"
The DLL phase-aligns the DRAM's internal DQ/DQS output timing with the external clock, compensating for propagation delay through the die's I/O circuitry. Decision Feedback Equalization (DFE), introduced in DDR5, compensates for inter-symbol interference — a signal-degradation problem phase alignment alone cannot fix.

DDR6's clocking is expected to split further to serve four subchannels instead of DDR5's two, requiring finer-grained per-subchannel clock alignment. DFE is expected to carry forward and likely strengthen, since inter-symbol interference gets worse — not better — as data rate roughly doubles again.

Some vendor discussion references a "Multi-Stream DRAM" (MS-DRAM) capability aimed at handling multiple concurrent data streams more efficiently. This is not a confirmed JEDEC term as of this writing and should be treated as speculative pending the ratified spec.

7. Bus Error Handling (Draft)

!!! danger "Two separate error domains — same principle as every prior generation"
On-die ECC protects data sitting in the DRAM array. CRC and parity protect data in transit on the bus. These remain independent mechanisms — a bit can be correct in the array, get corrupted on the way to the controller, and on-die ECC never sees it.

7.1 On-Die ECC (expected to continue as mandatory baseline)

DDR5 made on-die ECC a mandatory baseline feature. DDR6's much higher target density (up to 128 Gb/die) makes this baseline more necessary, not less, so it's expected to remain mandatory. LPDDR6 — the already-ratified mobile sibling standard — is explicitly documented as adding enhanced reliability and security features over LPDDR5, which is a reasonable signal for where desktop/server DDR6 is headed. It is not, however, a guarantee of identical mechanisms; LPDDR6 and DDR6 are related but separate specifications.

7.2 Write CRC and Command/Address Parity (expected to continue)

Both mechanisms — write-burst CRC verified against ALERT#-triggered retry, and command/address parity checking — are expected to carry forward conceptually from DDR4/DDR5. The specific implementation may change given DDR6's further command-bus encoding, but the underlying detect-and-retry pattern is expected to persist.

7.3 Read Path — Still an Open Question

!!! warning "Read-path CRC status is unconfirmed"
DDR4 and DDR5 both have no standardized CRC on the read path (DRAM → controller) — the standing weak link across every prior generation. Whether DDR6 closes this gap is one of the more consequential open questions in the draft. No pre-ratification source surveyed for this page confirms a native read-path CRC in DDR6. Assume the same weak link persists until the ratified spec says otherwise.

If it persists, read-path protection continues to depend entirely on system-level ECC — a separate mechanism computed by the memory controller using an extra ECC lane on ECC-capable modules, rather than anything native to the DDR6 protocol itself.

7.4 Summary Table

Error location	Detection mechanism (draft expectation)	Response
DRAM array (storage)	On-die ECC, expected mandatory	Auto-corrected inside the chip, invisible externally
Write data on DQ bus	Write CRC, expected to continue	`ALERT#`-style assertion → controller retries write
Command/address bus	C/A parity, expected to continue	`ALERT#`-style assertion → controller retries command
Read data on DQ bus	Unconfirmed	Likely silent corruption unless system-level ECC is present, same as DDR4/DDR5

8. Bandwidth (Draft)

Assuming each DIMM sums to a 64-bit-equivalent total channel width, consistent with the pattern DDR4 (single 64-bit channel) and DDR5 (2×32-bit) both follow:

Memory	Peak bandwidth (draft)
DDR6-8800	~70.4 GB/s
DDR6-17600	~140.8 GB/s by the same formula (some published previews cite ~134.4 GB/s — treat the exact figure as pre-ratification)

!!! note "Bandwidth, not latency, is the expected headline"
Every prior DDR generation delivered its real-world win in throughput and parallelism rather than reduced nanosecond latency, because internal timing parameters tend to scale up alongside clock speed. Early DDR6 coverage suggests the same pattern will repeat. Nothing here is confirmed until the ratified spec publishes timing parameters.

9. Timeline (As Currently Reported)

Milestone	Approximate timing
JEDEC circulates initial DDR6 draft specification	Late 2024
LPDDR6 (JESD209-6) ratified and published	July 2025
Desktop/server DDR6 platform validation (Intel, AMD, NVIDIA, DRAM makers)	Ongoing into 2026
Server/enterprise commercial availability	~2026 (industry estimate, not a JEDEC commitment)
Broader consumer availability	2027–2028 (industry estimate)

10. Study Checklist

[ ] Explain why DDR6 figures should be treated as directional rather than authoritative
[ ] State what LPDDR6 (JESD209-6, ratified July 2025) is and how it relates to — and differs from — desktop/server DDR6
[ ] Explain the reported four-subchannel DIMM structure and why the per-subchannel width is uncertain
[ ] Explain why DDR6's density roadmap (up to 128 Gb/die) is described as a capacity story rather than a bandwidth story
[ ] Explain what's expected to carry forward unchanged from DDR5 (on-die ECC baseline, on-module PMIC) versus what's still genuinely open (read-path CRC, exact voltage, bank-group count)
[ ] State the rough industry timeline consensus for server vs. consumer availability, and why it's an estimate rather than a JEDEC-confirmed date

References: Pre-ratification industry coverage of JEDEC JC-42.3 draft status; LPDDR6/JESD209-6 published July 2025; vendor roadmap disclosures from Samsung, SK hynix, Micron, Intel, AMD, and NVIDIA as reported through mid-2026. Verify all figures against the final ratified JEDEC DDR6 specification once published.