DDR5

Memory Updated Sep 2026

DDR5 SDRAM

The fundamentals of DDR5 SDRAM architecture — voltage, prefetch, bank topology, on-die termination, clocking, power delivery, and bus error handling.

!!! info "The basic DRAM cell"
DDR5 stores data the same way every DDR generation does: one transistor, one capacitor per bit, refreshed periodically because the capacitor leaks charge. Everything below describes the machinery built around that cell to get data in and out reliably at DDR5's operating speeds.

1. Overview

!!! abstract "Core specs"
Introduced 2020. Operates at 1.1 V. Data rates from 4800 to 8800+ MT/s. Standard desktop DIMM uses 288 pins.

Feature	DDR5
Introduction	2020
Typical voltage	1.1 V
Data rates	4800–8800+ MT/s
DIMM pins (desktop)	288
Prefetch / burst length	16n / BL16
Banks	32 in 8 bank groups
Channel width per DIMM	Two independent 32-bit subchannels
Signaling	POD-based, tighter tolerances

CPU
  │
Memory Controller
  │
Address/Command Bus
  │
DRAM Chips

Inside the DRAM chip:

Rows
──────────────
[row]
      │
      ▼
Sense Amplifiers
      │
      ▼
Column Select
      │
      ▼
I/O Drivers

2. Bank & Channel Topology

!!! note "Why bank groups exist"
A single bank can only service one command at a time — after an activate, it needs time to recover (tRC) before it can be activated again. As burst length and prefetch width grew, a single bank couldn't be fed fast enough.

DDR5 uses 32 banks organized into 8 bank groups. The much wider 16n prefetch (double DDR4's 8n) needs more banks in flight to stay fed, so DDR5 doubles the bank-group count again over DDR4.

The headline structural change: DDR5 splits each DIMM into two independent 32-bit subchannels, each with its own command/address bus:

DDR5 DIMM
32-bit channel
32-bit channel

This effectively doubles the number of outstanding operations a single physical module can service, which matters most for small, random accesses — the access pattern that dominates most real-world workloads, as opposed to long sequential streams.

3. Package-Level Details

!!! info "Package vs. DIMM"
A DIMM is a board populated with several DRAM packages. The specs below describe the DRAM IC package itself — the FBGA chip soldered or reflowed onto the module.

Aspect	DDR5
Package type	96/104-ball FBGA, ~0.8 mm pitch
Max practical die density	24–32 Gb+
Multi-die packaging	3DS/TSV stacking, common at server density
Command pins	Further encoded, reduced pin count
Added reliability pins	+ on-die ECC config, + per-subchannel CS
Power delivery to package	From on-DIMM PMIC (tighter, more local regulation)

Data width per chip (x4 / x8 / x16) follows the same convention as earlier generations, with one wrinkle: because each DIMM has two independent 32-bit subchannels, an x8 DDR5 chip feeds only one subchannel, so a minimum of 4 chips is needed just to populate both subchannels on a single rank.

4. On-DIMM Power Management

!!! warning "The biggest structural change in DDR5"
DDR5 moves voltage regulation from the motherboard onto the module itself via a Power Management Integrated Circuit (PMIC).

Motherboard
      │
   5V Input
      │
  PMIC on DIMM
      │
  DRAM Chips

This improves voltage regulation and power delivery at DDR5's higher speeds, but it also changes the failure domain: a dead PMIC takes down the whole module, whereas a board-level VRM issue (the model every prior generation used) was a separate, independently-diagnosable failure. It also means each DIMM now carries its own local power-conversion stage rather than relying entirely on the motherboard's regulation.

5. On-Die Termination (ODT)

!!! abstract "Why termination exists"
At multi-gigatransfer speeds, data and command lines behave like transmission lines. An unterminated line reflects signal energy back from the open end of the trace, and that reflection corrupts the next bit. ODT is switchable resistance built into the DRAM die (and host controller) that absorbs the reflection.

DDR5 carries forward the same DQ/DQS and command/address termination mechanics established in DDR4 — switchable resistor networks (commonly 240 Ω, 120 Ω, 60 Ω, sometimes 40 Ω) set via mode register commands — but pushes termination control down to the per-subchannel level, since at 4800+ MT/s even small impedance mismatches cause bit errors.

ODT mode	Purpose
`RTT_NOM`	Default termination during normal (non-write) operation
`RTT_WR`	Termination applied specifically during writes to that rank
`RTT_PARK`	Termination for a rank that is idle but must stay "quiet" without reflection-causing high impedance

6. DLL & Clocking

!!! abstract "Core idea"
The DLL phase-aligns the DRAM's internal DQ/DQS output timing with the external clock, compensating for propagation delay through the die's I/O circuitry. Without it, read data strobes drift out of phase with the clock as frequency increases and the controller can't reliably latch data.

DDR5's clocking duties split further to serve its two independent subchannels, requiring per-subchannel clock alignment rather than one shared clock domain per DIMM.

Key DDR5 addition: Decision Feedback Equalization (DFE) on the receiver side, compensating for inter-symbol interference — bit smearing caused by bandwidth limits in the channel. This is a signal-degradation problem that phase alignment (the DLL's job) alone cannot fix; DFE actively reshapes the received signal to undo the smearing.

7. Bus Error Handling & ECC

!!! danger "Two separate error domains"
On-die ECC protects data sitting in the DRAM array. CRC and parity protect data in transit on the bus. These are independent mechanisms — a bit can be correct in the array, get corrupted on the way to the controller, and on-die ECC never sees it, because on-die ECC runs before data leaves the chip.

7.1 On-Die ECC (array-side) — new mandatory baseline

Internally stores extra parity alongside data — typically SECDED (single-error-correct, double-error-detect) over a 128-bit data + 8-bit ECC block, though the exact code is vendor-specific; JEDEC mandates SECDED-equivalent coverage, not a fixed algorithm.
Computed on write, checked and corrected on read, entirely inside the die — invisible on the external pins unless a vendor exposes error counters via mode registers.
Became a mandatory baseline feature in DDR5 — the first DDR generation to require it — because raw bit error rates rose as density increased at shrinking geometries.
Not a substitute for system-level ECC — it does nothing for errors introduced after data leaves the die.

7.2 Write CRC (data bus, host → DRAM)

Controller computes a CRC over the write burst and sends it alongside the data.
DRAM independently computes its own CRC on what it received and compares.
Mismatch → DRAM asserts ALERT# low → controller retries the write (it still has the original data buffered).

7.3 Command/Address Parity

Every command/address transfer carries a parity bit. A parity violation also asserts ALERT#, and the controller re-issues the command — this matters more than a data error would, since a corrupted address bit could activate the wrong row entirely.

7.4 Read Path — the Weak Link

!!! warning "No native CRC on reads"
DDR5 has no standardized CRC on the read path (DRAM → controller). Writes are protected because the controller can trivially retry — it still holds the data. Reads have no equivalent fallback in the base spec.

Read-path protection instead depends entirely on system-level ECC — a separate mechanism computed by the memory controller, using an extra ECC chip/lane on ECC-capable DIMMs (the classic 72-bit-wide-instead-of-64-bit module). Without system-level ECC, a bit flip on the read bus that nothing else catches is delivered to the CPU as silent corruption.

7.5 Summary Table

Error location	Detection mechanism	Response
DRAM array (storage)	On-die ECC	Auto-corrected inside the chip, invisible externally
Write data on DQ bus	Write CRC	`ALERT#` asserted → controller retries write
Command/address bus	C/A parity	`ALERT#` asserted → controller retries command
Read data on DQ bus	None	Silent corruption unless system-level ECC is present
Multi-bit error beyond on-die ECC's correction capability	Reported uncorrectable (if exposed) or nothing	Depends entirely on system-level ECC above it

8. Refresh and Voltage Training

DDR5 adds Same Bank Refresh (REFsb) — the ability to refresh one bank while other banks in the same group stay accessible, reducing the throughput hit refresh operations otherwise cause. It also continues VrefDQ training (introduced as standard in DDR4) with tighter tolerances, needed to keep the reference voltage accurately calibrated at DDR5's higher speeds.

9. Bandwidth Reference

Assuming a single 64-bit-equivalent channel (DDR5's two 32-bit subchannels sum to 64 bits total per DIMM):

Memory	Peak bandwidth
DDR5-4800	38.4 GB/s
DDR5-5600	44.8 GB/s
DDR5-6400	51.2 GB/s
DDR5-8800	70.4 GB/s

!!! note "Latency vs. bandwidth"
DDR5's latency in nanoseconds is not dramatically lower than DDR4's, because internal timing parameters scaled up along with clock speed. For most desktop workloads, DDR5's advantage is throughput and parallelism, not reduced latency.

Modern desktop CPUs typically have two memory channels; servers may have 8, 12, or more.

10. Study Checklist

[ ] Explain why capacitor leakage requires periodic row refresh
[ ] State DDR5's voltage, prefetch, and bank-group organization
[ ] Explain why DDR5 splits each DIMM into two 32-bit subchannels
[ ] Describe the on-DIMM PMIC change and its failure-domain implications
[ ] Explain what RTT_NOM, RTT_WR, and RTT_PARK each control
[ ] Explain what DFE adds that the DLL's phase alignment alone cannot fix
[ ] Distinguish on-die ECC from system-level ECC — what each protects and what neither protects
[ ] Trace what happens when write CRC or C/A parity detects an error (ALERT# → retry)
[ ] Explain why the read path has no native CRC and what closes that gap
[ ] Explain Same Bank Refresh (REFsb) and why it matters for throughput

References: DDR5 JEDEC specification (JESD79-5).